A Convolution based Global Placement for FPGAs

Elias de Almeida Ramos, Vitor Hugo Fuerstenau Maciel, Germano Girondi and Ricardo Reis

FBM v2: A Simple and Even Faster Algorithm for Placement Legalization

Jorge Ferreira, Paulo Butzen and Ricardo Reis

Power-Delay Optimized Logic Cell Library for Monolithic 3D-Integrated Circuits

Juliano Cavinato Zanelli, Carolina Metzler and Ricardo Reis

Proposal and Evaluation of Pin Access Algorithms for Detailed Routing

Marcelo Danigno, Paulo Butzen, Jorge Ferreira, André Oliveira, Eder Monteiro, Mateus Fogaça and Ricardo Reis

On Democratizing Hardware Design: UFRGS/FURG Contributions to The OpenROAD Project

Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Vitor Bandeira, Paulo F. Butzen and Ricardo Reis

Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS

Rodrigo Wuerdig, Vitor Lima, Filipe Baumgratz, Rafael Soares and Sergio Bampi

A Smart Vibration Monitoring System for Maintenance Prediction of Electrical Motors

Marcelo Romanssini, Felipe A. Quirino, Gunnar G. Ávila, Felipe B. Fava, Lucas Compassi Severo, Paulo C. Aguirre and Alessandro G. Girardi

True Random Number Generator based on Oscillator Rings Implemented in FPGA

Estevan Lima and Sibilla França

An Embedded System for Monitoring Industrial Air Dehumidifiers using a Mobile Android Application for IEEE 802.11 Networks

Jefferson Rodrigo Schuertz, Erik de Oliveira Rosa, Marcos Fernando Fragoso, Lincoln Grabarski, Allan Christian Krainski Ferrari and Carlos Alexandre Gouvea da Silva

A Workbench for Testing and Simulation Faults in Three-phase Electric Motors with Intelligent Electronic Device and Microcontrolled System

Jefferson Rodrigo Schuertz, Giovanni Faria, Michel Fernandes Peres, Osmar Moreira da Silva Neto, Edson Leonardo dos Santos and Carlos Alexandre Gouvea da Silva

Complexity Reduction for Prediction Unit Decision in HEVC Transrating

Matheus Lindino, Thiago Bubolz, Bruno Zatt and Guilherme Correa

ASIC Solution for the Directional Intra Prediction of the AV1 Encoder Targeting UHD 4K Videos

Luiz Neto, Marcel Corrêa, Daniel Palomino, Guilherme Corrêa and Luciano Agostini

Evaluation of Memory Requirements in VVC Encoders

Arthur Cerveira, Bruno Zatt and Felipe Sampaio

Performance Evaluation of Depth Modeling Modes for 3D-HEVC Depth Maps Intra Coding

Christopher Moura, Mário Saldanha, Gustavo Sanchez, César Marcon, Luciano Agostini and Marcelo Porto

Distortion-Aware Fast Intra Prediction for ERP 360 Video Coding

Iago Storch, Bruno Zatt, Luciano Agostini, Daniel Palomino, Luis A. da Silva Cruz and Sergio Bampi

Behavioral Modeling of Power Amplifiers Using Perceptrons with Complex Activation Functions

Luiza Beana Freire, Luis Schuartz, João Dias and Eduardo de Lima

Polar Volterra series applied in modeling of competing dual-band power amplifiers

Bianca Oliveira, Luis Schuartz and Eduardo Lima

A Fully Integrated ULV Capacitor-Based DC-DC Converter for Artificial Light Energy Harvesting

Luiz Antônio Da Silva Jr., Lucas Compassi Severo and Alessandro Girard

Review on Dynamic Comparators

Erik Pinto Martins, André Luiz Aita and Leonardo De Lima Ferreira

Exploring Parallel Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly

Guilherme Ferreira, Leandro M. G. Rocha, Eduardo Costa and Sergio Bampi

Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization

Pedro Pereira, Guilherme Paim, Patricia Ucker, Eduardo Costa, Sérgio Almeida and Sergio Bampi

Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes

Henrique Seidel, Morgana Macedo Azevedo Da Rosa, Guilherme Paim, Eduardo Da Costa, Sérgio Almeida and Sergio Bampi

Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers

Leandro Mateus Giacomini Rocha, Morgana Macedo Azevedo Da Rosa, Guilherme Paim, Eduardo Da Costa and Sergio Bampi

An Analysis of Voltage Scaling Applied to Approximated Full Adders

Pedro Aquino Silva and Cristina Meinhardt

Bit width Exploration for Energy-efficient Image and Video Processing

Talita Borges, Cristina Meinhardt, Leonardo Soares and Vagner Rosa

Parallel Hardware Architecture for the HEVC Deblocking Filter

Marcos R. P. Bueno and Bruno Zatt

ASIC implementation of FME HEVC interpolation filters using approximate computing

Rafael da Silva, Ícaro Siqueira, Ricardo Reis and Mateus Grellert

Approximate 4x4 Sum of Absolute Transformed Differences Hardware Accelerator

Matheus Stigger, Victor Lima, Leonardo Soares, Cláudio Diniz and Sergio Bampi

Comparative evaluation of Dual Interlocked Cell in 32nm CMOS and 7nm FinFET

Maria Eduarda de Melo Hang and Cristina Meinhardt

Evaluation of Process Variability in DPA Countermeasure Topologies

Plínio Finkenauer, Rafael Soares and Vinícius Valduga de Almeida Camargo

Exploring Parallel Programming in Automatic Test Pattern Generation

Clayton Rodrigues Farias and Paulo F. Butzen

Simple Essay to Assess the Impact of Different Methods on Reliability Analysis

Glória Claro, Clayton Farias, Matheus Pontes, Rafael B. Schvittz, Leomar S. da Rosa Jr. and Paulo F. Butzen

A Comparative Analysis of Performance and Sensitivity to Radiation of XORs in 16 nm CMOS and FinFET Technologies

Rafael Neves de Mello Oliveira and Cristina Meinhardt

Robustness enhancing inverters on Full Adders and Low Power applications

Leonardo Moraes, Alexandra Zimpeck, Cristina Meinhardt and Ricardo Reis

Dr. Guillaume Ferré, IMS, Bordeaux, France

Title: A Novel Approach to Process the Multiple Reception of Non-Orthogonal LoRa-Like Signals

Abstract: LoRa is a chirp spread-spectrum modulation that operates in industrial, scientific, and medical (ISM) free bands. The modulation has been developed for low power and long-range wireless Internet of Things (IoT) communications. Operating in unlicensed bands requires connected objects to reduce their energy consumption. Thereby, it is very likely that their access to the radio channel is random, which leads to an increase in the probability of packet collisions. In this paper, we design a new receiver able to decode several IoT LoRa-Like signals simultaneously received on the same channel and with the same spreading factor which leads to destructive collisions. Based on the particular structure of the superposed received signals and the Successive Interference Cancellation (SIC) algorithm, we propose a novel approach to detect, synchronize and decode each of them iteratively.

Short Bio: Dr. Guillaume Ferré graduated in electronic and telecommunication engineering (ENSIL) at the University of Limoges (France) in 2003 and received the Ph.D. degree in 2006 from the Limoges University of Technology in the field of digital communications and signal processing. From 2006 to 2008 he was postdoctoral researcher at the Limoges XLIM laboratory and then at the IMS laboratory in Bordeaux. Since 2008 he is associate professor at ENSEIRB-MATMECA, an engineering school of Bordeaux INP. After several administrative responsibilities in the Telecommunications Department of ENSEIRB-MATMECA, Guillaume Ferré is now the Director of Industrial Relations at ENSEIRB-MATMECA. He carries out his research activities within the IMS laboratory in the "signal and image" team. These fields of research concern the circuits and systems for digital communications, it includes: - Signal processing and digital communications for 5G - Digital enhancement for wideband power amplifiers and time interleaved analog to digital converters. Guillaume Ferré is the author of more than a hundred papers in international conferences. He is also author of 4 patents. He currently supervises 5 PhD students with a significant part of industrial research activities. He is member of several Technical Program Committees (ICT, ICECS, etc.). In the IMS laboratory he holds the position of Vice-President of the Scientific Council. He is the Principal Investigator (PI) of many national and international projects, at the local level he is responsible for two research activities related to IoT, including one to investigate on the smart campus.

Prof. Dr. Fernando Silveira, Universidad de La Republica Montevideo, Uruguai.

Title: How much it cost to help our circuits to age gracefully? or Can our circuits age gracefully and simultaneously improve the performance?

Abstract: Analog circuit design is characterized by the large number of degrees of freedom and large number of opposing performance aspects that the designer must permanently trade-off. In this talk we will consider the case of radio frequency blocks, such as low noise amplifiers, voltage controlled oscillators and particularly power amplifiers, key for current smart objects wirelessly connected. We will first illustrate the approach of design space exploration for handling the performance trade-offs in RF circuit design in an informed way. Then we will focus in adding, the often overlooked dimension, of aging and reliability. How these circuits age ? How to, efficiently, handle the performance trade-offs in a reliability aware approach ? For humans, to age gracefully, usually imply to resign some things and some sacrifices. In the circuit world, how much it cost in performance to help our circuits to age gracefully ? May be that usual reliability directives could be a diet more strict than required for our circuits ? We expect to discuss, interactively, with the audience these topics.

Short Bio: Fernando Silveira received the electrical engineering degree from Universidad de la República, Montevideo, Uruguay, in 1990, and the M.Sc. and Ph.D. degrees in microelectronics from Université catholique de Louvain, Louvain-la-Neuve, Belgium, in 1995 and 2002, respectively. He is currently a Professor with the Electrical Engineering Department, Universidad de la República. His research interests include the design of ultra-low-power analog and RF integrated circuits and systems, in particular with biomedical application. In this field, he has co-authored one book and many technical papers. He has had multiple industrial activities including leading the design of an application specified integrated circuit for implantable pacemakers and designing analog circuit modules for implantable devices for various companies worldwide, field in which he continues to do consulting. He was member of the Technical Advisory Board of Gtronix, Inc, USA from 2006 to 2010, received the “Ingeniero Destacado” (Distinguished Engineer) award by the Uruguayan Association of Engineers in 2007 and was a member for 2011-2012 of the Distinguished Lecturers Program of the IEEE Circuits and Systems Society. Since 2017 he is a member of the Honorary Committee of the National Researchers System of Uruguay.

Cache Efficiency Evaluation for Intra and Inter Frame Decoding

Garrenlus Souza, Sergio Bampi and Felipe Sampaio

Analysis of the Emerging Versatile Video Coding Standard Complexity and Compression Efficiency

Icaro Siqueira, Guilherme Correa and Mateus Grellert

Regular Interpolation Filter Hardware Architecture for the AV1 Video Coding Standard

Daiane Freitas, Rafael da Silva, Ícaro Siqueira, Cláudio Diniz, Ricardo Reis and Mateus Grellert

8K UHD @60fps Low-Power and Real-Time HEVC Deblocking Filter Architecture

Roberta de Carvalho Nobre Palau, Jones Goebel, Eduardo Zummach, Daniel Palomino, Guilherme Corrêa, Marcelo Porto and Luciano Agostini

An AV1 Constrained Directional Enhancement Filter Architecture for 4K@60fps Videos

Eduardo Zummach, Roberta Palau, Jones Goebel, Luciano Agostini and Marcelo Porto

Victor Grimblatt, Synopsys, Chile.

Title: The Application of Technology in the Agribusiness

Abstract: The world needs more food. More and more population with less arable land is already a big challenge for the agriculture. Technology can be a major actor to solve this issue. However, this is not yet the case as the technology has been far from the agribusiness, especially in Latin America. Only big farmers have approached technology. In Latin America, where agriculture plays an important role in the economy, technology is far from being deployed in the field. This talk will provide an overview of how technology and IoT are impacting and solving agribusiness issues, what are the next challenges and how Latin America is adopting technology in the agribusiness domain.

Short Bio: Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore, he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and Circuit design Sub-Committee for ICECS. He is also is Program Co-Chair of FoodCAS. Since 2018 he is Chair of LASCAS Steering Committee.

Dr. Elkim Roa, Universidad Industrial de Santander, Colombia

Title: Low-Energy Always-On Subsystems and Circuits Enabling Security in RISC-V based SoCs

Abstract: The talk will present a family of 32-bit RISC-V based SoCs featuring a power management unit (PMU), a debug module, an AON sensor circuitry, security instances, and AES acceleration. The talk would touch on some highlights on energy issues related to inefficient communication between a master and a time-constrained peripheral in standard bus approaches. In addition to presenting circuit and system details, the talk would also add a review on the integration of the SOC using a meta-programming language (Chisel) to automate specification, verification, and construction. The SOC and the integrated IP was validated using a proposed verification scheme combining two different domains, functional and formal, converging to exclusive error detection without requiring apriori large test sets.

Short Bio: Elkim Roa received the B.S.E.E. degree from Universidad Industrial de Santander at Bucaramanga, Colombia, in 1999, the M.S.E.E. degree from the University of Sao Paulo in 2003, Sao Paulo, Brazil, and the Ph.D. degree in electrical engineering from Purdue University in 2014 where he was a Fulbright scholar. From 2014 to 2016, Elkim was with Rambus Inc. where he was engaged in high- speed SERDES front-end design. Currently, he is an associate professor at Universidad Industrial de Santander, Colombia. His research interests include circuits and VLSI design for security, front-end circuits for high-speed interfaces and low-energy and efficient computing.

Dr. Sergio Bampi, UFGRS, Brasil

Title: Near-Threshold CMOS Circuits : Frontiers in Ultra-Efficient Analog and Mixed-Signal CMOS Integrated Circuits

Abstract: Promising opportunities for research on heterogeneous Internet-of-Things (IoT) devices lie at the energy-bottom floor, where CMOS is still an unbeatable and flexible technology to make the internet of “everything” possible and cost-effective. Near-threshold computing (NTC) in CMOS is a promising alternative for any SoC application which can tolerate or benefit from very wide voltage-frequency scaling (VFS). The digital blocks in SoCs may operate at very different power-performance modes, from sub-MHz to peaks of hundreds of MHz, which requires CMOS digital libraries targeted for NTC. The analog and RF content on IoT chips will be even more crucial, from a power-savings standpoint. In IoT it is best to avoid using costlier CMOS nodes, those still closer to the end of the 2-D transistor and IC scaling. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific logic design techniques to be applied in digital CMOS. This talk addresses a method to design CMOS digital circuits for a wide dynamic range of VFS, and targets near-threshold for best energy-efficiency. Our previous work on 65nm CMOS has demonstrated 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their system operating modes. The results in CMOS were obtained using the minimal cycle time achievable at each supply voltage, down to very low 200 mV supplies. The strategy for transistor sizing in digital cells and static noise margin maximization at NTC will also be addressed in the talk. Results in a mixed-signal, mostly-digital CMOS design approach, to design ultra-efficient OTA (operational transconductance amplifier) with digital gates will also be shown, to motivate a radically new approach to analog design. The seminar seeks to stimulate system-level and circuit-level design approaches for IoT nodes, as the presenter is available to discuss LP-LV digital CMOS, mixed-signal, and RF aspects of CMOS systems on-IoT-devices.

Short Bio: Sergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS, 1979), and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics design fields at the Informatics Institute, member of the faculty since 1986. He served as Graduate Program Coordinator (2003-2007), head of research group and projects, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff, and a visiting research faculty at Stanford University (1998-99) in the USA. His research interests are in the area of IC design, ultra-low power digital design, dedicated complex algorithms, architectures, and ASICs for image and video processing, RF CMOS design and mixed signal IC designn for IoT. He has co-authored more than 400 papers in these fields and in MOS devices and EDA. He is a senior member of IEEE, SBC, and SBMICRO societies. He was Technical Program Chair of IEEE SBCCI Symposium (1997, 2005), SBMICRO (1989, 1995), IEEE LASCAS (2013), VARI 2016 Workshops and Conferences.

Gyuszi Suto, Intel, USA

Title: Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling.

Abstract: VLSI Physical Design Process Rules put complex constraints on how the transistors and interconnect (wires and vias) can be laid out in order to achieve high yield. In the past, the rules mostly constrained the sizes - and spacings between pairs – of these objects. In the advanced process nodes (7nm, 5nm) the rules are very complex, multiple objects arranged in peculiar spatial relationships. This talk will describe a new language that can describe patterns of various complexity in a compact, elegant and readable form.

Short Bio: Graduated in 1987 from Universitatea Technica in Cluj-Napoca, Romania. In the 1987-1993 period, he worked in various companies developing Physical Design CAD and compilers for supercomputers. In 1993, he joined Intel Corporation in Hillsboro, Oregon, USA. He has been involved in VLSI Physical Design ranging from placement, routing, DFM. Since 2010, his focus has been VLSI design rule modeling for advanced nodes. He was part of the C++ standardization effort until 1998. At Intel, he taught C++ and organized yearly programming contests and S/W conferences. His hobbies are: skiing, windsurfing, karate, hiking, photography, music.